Aug 18, 2016

30 MHz DIY Signal Generator (part 1)

A year ago I started this simple, microcontroller based DIY signal generator project which was capable for approximately 60_kHz sampling rate. However, that ended up to be quite boring becase I need test signals with higher bandwidth in my projects and there's already couple of similar MCU based signal generator projects on the internet. One idea leaded to another, and now I have dual channel, 90_MS/s, 30_MHz, 16-bit self-made arbitrary waveform generator (AWG). This won't be a complete step-by-step tutorial to build a similar one, but I'll try to explain enough details to give a good overview about the system. Also, the HW design and source code will be released, if someone wants to build one or even develop it further!

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The user interface (UI) is managed mostly by the Atmel ATmega microcontroller. The signal generation itself is done in FPGA, which controls also the LCD screen, and couple of other miscellaneous tasks. The digital signal goes from the FPGA to the high-performance DAC through the 2x 16-bit parallel bus, and the analog signal passes through the low-pass filter, to the high speed op-amp and output BNC connectors. The low-pass filter is needed to remove the unwanted alias frequencies.

Analog bandwidth__30 MHz
Sample rate90 MS/s
Channels2 (+one internal modulation gen. / ch.)
Voltage swing±8 V (±4 V to 50 Ω load)
WaveformsSine, Square, Triangle, Saw, Noise, Arbitrary__
ModulationFM, AM, PM, Frequency sweep
Others2.8" TFT touch screen,
3 rotary encoders,
10 MHz clock reference input (BNC),
2.5 PPM internal clock reference,
USB remote control & SW update

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The first prototype was built by using a Lattice XO2 breakout board (~$25) and self-made ATmega328P development board. The DA converter was implemented with two 8-bit R2R ladder DACs. There was no LCD or control knobs attached yet, but all the commands was given via virtual COM port (FTDI FT232RL) to the MCU, which controls the FPGA via SPI bus.

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The next step added the LCD screen, control knobs and a frontend low-pass filter & amplifier (TI_THS3001) testing board to the prototype. The DAC component (AD9747) was not tested in this prototype, because the breakout board just for that would have been quite expensive due to the price of the DAC IC (~$30). Instead of physical breakout board, the DAC and the analog front-end was simulated by using Agilent Advanced Design System, and the simulations ended up to match pretty well to real-world performance tests.

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Download schematic:
PDF File (rev 1.0)
Proteus 7.7 Schematic file (rev 1.0)

As you may notice, there is no separate JTAG header for the FPGA, but there's a ISP header for flashing the ATmega MCU. After flashing the Chip45boot2 bootloader to the MCU, the ISP header isn't needed anymore. The Lattice XO2 breakout board has a FTDI FT2232H USB interface IC which is programmed to USB-JTAG bridge configuration. The same IC is utilized also in this design, but more of that, it has also a USB-UART bridge functionality, so both, the MCU and the FPGA can be programmed via the single USB connector. The USB-UART bridge also allows the debugging and remote control features for the MCU.

The schematic design of the front panel leds & knobs may look a bit strange at the beginning, but the idea was to use as few MCU pins as possible for controls. All of the signal wires are connected to ADC pins of the MCU, which switches these pins very rapidly between the input mode (reading the values of knobs) or the output mode (feeding current to the leds). Depending on the voltage value, the MCU deduces the position of the switches. More common way would have been to place an extra MCU to front panel PCB for knobs & leds and the communication would pass through I2C bus, but again, this solution was chosen to keep the design as simple as possible (and to try something new). As an after thought, it works quite ok after tuning the ADC treshold values, but in my next AWG project I'd use a separate MCU for controls.

As the XO2 FPGA has a quite nice clock manipulation features built-in, I used a temperature compensated crystal to provide an accurate clock reference for the signal generator core. However, if even that isn't accurate enough or the clock of the different devices needs to be synchronized, there's also a input BNC connector for the external 10 MHz clock reference, and the internal clock MUX of the FPGA selects the clock, that is selected from the UI menu.

To keep the design as simple as possible, there is no variable gain amplifier or even separate DAC for offset leveling. This compromises in the resolution of the AWG, since the smallest possible voltage step is 16_V_/_2^16_=_0.24_mV in any voltage or offset scale.

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The design was fitted into 50 x 100 mm 2-layer PCB, which was ordered from ITead Studio. There was only one bug, which was easily corrected with a piece of copper wire, so I decided not to order a new revision. Also the 5 V linear regulator, next to the power connector was replaced with SMPS module, which gives a lot better efficiency. The front-end op-amps still have linear regulator for the best possible noise performance. Power rails of the DAC are well filtered and regulated with LDO regulators, so the switching noise wouldn't pass to the signal outputs.

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The project box (Bahar BDA-40004-W200) was ordered from AliExpress, and modified for all the knobs, connectors, leds and the display. The layout was designed in 3D modelling software to make sure that everything fits nicely and the placement looks logical. Someone may like separate buttons, but I'm a fanboy of rotary encoders, so there's three of them! One controls the selected menu item, another the digit of the selected value and third knob controls the value of the selected menu item/digit.

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All the necessary pieces fitted into that project box. The main power supply is implemented by using IEC power connector with fuse holder & switch and 230 V to 2x15 V toroidal transformer. AC voltage goes to the PCB with fuses, MOVs (over-voltage protection), rectifier and bypass capacitors. +-21 VDC voltage passes to main PCB. The transformer with 2x 10-12 VAC outputs would be ideal, but I happened to have this 15 VAC model already, so it shall be good enough, althoug the output voltage is a bit high.

WARNING - Do not attempt construction of the power supply if you do not know how to wire mains equipment.

Well, that was quite broad description about the project. The Part 2 will include the PCB design files, source code, description about the program and performance measurements. Please, Tell me in the comments, what else you want to be included into Part 2!


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    1. hi Petteri Liikkanen
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  2. Thank you for this excellent project! Do you have an idea when the second part could be expected? I am just so anxious about trying it out.

    1. Thanks! Good to hear that there's interest for part 2. Lately I've got time only for smaller projects, but I'll try to write the part 2 when possible. Also the program works but is still quite..lets say..spaghetti code. Would be nice to release a bit more refined version, but we'll see.. :) It won't be a complete step-by-step guide, but I think that anyone with good electronics knowledge should be able to at least reproduce it. If you have a Twitter, I'll inform about my new posts also there.

    2. First of all very nice project... I want to build that machine too :). But can you please make part 2 of the project i really need code and gerber files to build it...
      Kind Regards

  3. Electronic advancements has improved the quality of technical standards. This generator looks a good addition in the computers technology. I hope we wll soon see the next version of it with more capacity.

  4. Is this project still going on? Very nice project.

  5. where is part 2 this project is so exquisit

  6. How many samples per wave ? What is max and min frequency ? How do you handle sample rate below 1Hz. Do you store samples in the memory or compute them ? Thanks for sharing

  7. This comment has been removed by the author.

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  12. hey Hi
    I hope u be as well as always
    Would you pls tell more about what is going on inside the FPGA?


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